This invention relates to addressing techniques used for bus oriented computer systems. More particularly, this invention relates to an automatic addressing technique for flexibly specifying the individual addresses of a plurality of devices coupled to an information bus.
Bus oriented computer systems are known in which individual devices connected to an information bus are assigned unique addresses specifying the location of each device in a computer system. Typically, individual devices are provided with a mechanical, electrical or electromechanical device capable of being set to provide a unique address for the device. For example, in some known arrangements, each device is provided with jumper terminals which can be connected to an appropriate voltage (e.g., ground) in such a manner that the voltage level on the combined collection of jumper terminals uniquely specifies the physical address of that device, usually using a binary numbering system. In still other known system, manually actuatable switches are employed for the same purpose. In both types of arrangement, the specification of a unique device address requires that a user, usually a technician, manipulate the address specifying device, which creates the possibility for human error in initially configuring the system. In addition, to reconfigure such a system, for example by adding more bus devices, the user must check the setting of each device (or a master list on which the individual addresses are recorded) in order to ensure that the new addresses to be assigned to the additional devices do not duplicate already used addresses.
Still other systems employ active electronic devices capable of responding to interrogation from a host computer by setting a device address generated by the host computer and transmitted thereto over the information bus. Such arrangements require additional active electronic circuits in the bus devices, and also require special programming capability in the host computer to generate the individual device address values and transmit such values to the individual bus devices. Also required is a routine for establishing that an address transmitted to a device was correctly received and stored by that device. This type of arrangement required a relatively sophisticated programming approach and is prone to both software and signaling errors.
The invention comprises an automatic addressing technique for specifying the individual unique addresses of an array of devices which is relatively simple and inexpensive to implement, highly reliable in operation, capable of establishing any address sequence required in a given application, and highly compatible with highly configurable computer system.
From a first aspect, the invention comprises a method of specifying the physical address of a plurality of devices each requiring a unique address in an array, the method including the steps of selecting the individual desired address sequence, creating an anchor pattern representing an initial device address, the anchor pattern having a plurality of multi-bit rank ordered fields each having a superior end position and an inferior end position, creating a bit pattern representing the next address in the sequence by shifting the bit pattern in each field in the direction of the superior end position of that field by an integral multiple (preferably unity) of one rank and relocating the superior end rank position bit of the pattern to the inferior end rank position, and continuing the step of creating a bit pattern representing the next address until the last address in the sequence is attained. For an anchor pattern comprising N bits, the number of the fields can range from N to i, where i is the minimum number of bits required to uniquely specify a total number of J devices. Each address is specified with a bit of predetermined rank from each of the i fields.
From an apparatus standpoint, the invention comprises a multiconductor bus device for specifying a unique physical address for each of a plurality of J devices in an array in accordance with a desired address sequence, the bus device comprising N conductors arranged in parallel and grouped into i fields, where i is the minimum number of bits required to uniquely specify J devices, each field having a plurality of rank ordered bits with a superior end position and an inferior end position, the physical address for each device being determined by i bit values selected from one conductor of each field, and a plurality of transform elements each having an input coupled to the N conductors for converting a physical device address presented at the input thereto to the next physical device address at the output thereof, each transform element including means for shifting the bit pattern in each field of a physical device address presented at the input by an integral multiple (preferably unity) of one rank and relocating the superior end rank position bit of the input address to the inferior rank position of the output address. The number of bit values i used to determine the physical address for each device may be increased up to a value of N, if desired, to create additional potential address sequences.
Each transform element preferably comprises a plurality of N input terminals, a plurality of N output terminals and a plurality of N conductive paths coupled between the input terminals and the output terminals, one path coupling the input terminal corresponding to the superior end rank position of each field to the output terminal located at the inferior rank position of the corresponding field.
From a different method aspect, the invention comprises a method of producing a multi-bit anchor pattern capable of transformation into a desired sequence of physical device addresses, each address comprising a plurality of bits each selected from a different one of a plurality of rank ordered multi-bit fields, each bit in each address corresponding to a preselected rank in the associated multi-bit field. The method proceeds by selecting a desired address sequence, converting each address of the desired sequence to a multi-field binary equivalent having a number of fields equal to the number of bits comprising each address, and arranging the bits in each binary equivalent field in a sequential order related to the manner in which the anchor pattern is transformed into the desired sequence of physical device addresses.
The invention provides a highly reliable device addressing capability which is extremely simple to implement, requiring only passive electrically conductive paths arranged in a repeated predetermined pattern in order to effect the sequential address transformations. Since the desired sequence can be unlimited, the invention is extremely useful and effective is bus oriented computer systems which are intended to be highly configurable. Moreover, the specification of a desired address sequence is completely determined once the anchor pattern has been established for a given desired sequence.
For a fuller understanding of the nature and advantages of the invention, reference should be had to the ensuing detailed description taken in conjunction with the accompanying drawings.